The SION engineering portfolio is where students accumulate evidence — not certificates. Every project is reviewed by practicing engineers and joins your permanent portfolio of demonstrable engineering ability.
Projects are organised by specialisation — ASIC, Verification, and FPGA. Every project card documents the full engineering arc: problem, specification, architecture, tools, implementation, challenges, debug, results, skills demonstrated, and deliverables.
RTL · Synthesis · Timing
UVM · Coverage · Assertions
RTL · Board · Live Demo
Design a multi-stage pipelined arithmetic block with configurable data widths, hazard handling and forwarding. Full RTL through synthesis and timing closure.
Design an AMBA-style bus interface block with masters, slaves and interconnect. Implement, simulate and integrate at subsystem level.
Build a complete UVM environment — driver, monitor, agent, sequencer, scoreboard — for a mid-complexity digital IP. Close functional coverage to defined targets.
Verify a subsystem containing multiple IPs. Build layered coverage models, run regression, triage failures, and drive coverage closure.
Design an FPGA system from RTL through timing closure to a live board demonstration. Integrate IP, close timing, program the bitstream and demo on real hardware.
Bring up a defined interface on an FPGA board, debug signal-integrity and functional issues, and instrument with internal debug cores.
Every project produces the same set of deliverables — because that's what hiring engineers look for. By the end of the program, students have a coherent, portable, verifiable portfolio of their capability.
Don't graduate with just a certificate — graduate with a portfolio real engineers can read.