How an SoC goes from specification to silicon.

Every chip you've used — the processor in your phone, the SSD controller in your laptop, the accelerator in a data centre — travelled through the same conceptual flow. Nine stages, from a written spec to a working silicon device.

Here is that flow, written for engineering graduates trying to understand where they'll actually contribute.

Stage 01 · Specification.

Everything begins with a written spec. What is the chip supposed to do? What are its performance, power and area targets? What interfaces will it expose? Which markets will it serve?

Architects, product managers and system engineers own this stage. Fresh RTL engineers rarely write specs — but great RTL engineers read them carefully, catch ambiguity, and flag missing corner cases.

Stage 02 · Microarchitecture.

Specs become block diagrams. How is the design partitioned? Which functions live in which blocks? What are the interfaces between them? How are pipelines organised? Where do we register signals? Where do we accept latency to buy timing?

Senior designers own microarchitecture. Fresh RTL engineers typically own the micro-microarchitecture — the internal structure of a specific block.

Stage 03 · RTL design.

Verilog or SystemVerilog code. This is where RTL engineers spend the majority of their attention — coding the logic, running simulations, iterating.

Stage 04 · Verification.

Simultaneously with RTL, verification engineers build environments that systematically prove the RTL matches the spec. UVM environments, assertions, coverage — all running in parallel to design.

Verification consistently outweighs design in modern SoCs — often more engineers, more compute, more schedule.

Stage 05 · Synthesis.

The RTL — plus a set of timing, power and area constraints — feeds a synthesis tool that turns it into a gate-level netlist. The synthesised design is what will physically exist.

Fresh engineers read synthesis reports carefully. What did the tool actually build? Did it infer the flops you expected? Are the critical paths where you'd predict?

Stage 06 · Static Timing Analysis.

Every timing path — from every flip-flop, through combinational logic, to every other flip-flop — must be fast enough. STA is the discipline that proves it. Setup time. Hold time. Constraint definitions. Timing closure.

STA is where good RTL and bad RTL diverge visibly. Bad RTL cannot be rescued by tool tuning.

Stage 07 · Physical design.

The netlist is placed on the die, wires are routed, clocks are distributed, DRC/LVS is checked. Physical designers own this — a deep back-end specialisation.

Stage 08 · Tape-out & fabrication.

The finished design is sent to a foundry. Mask sets are built. Silicon is fabricated over weeks to months. There is no going back after tape-out — which is why verification was so thorough.

Stage 09 · Bring-up & validation.

Silicon returns. Post-silicon engineers validate it in real systems. Bugs — if any — must be worked around in software, in firmware, or in the next revision.

Where you'll contribute.

• Fresh RTL engineer: Stage 03 primarily. Increasingly Stages 02 and 05 with experience.
• Fresh verification engineer: Stage 04 primarily. Often reads Stages 01 and 03 daily.
• Fresh FPGA engineer: The full flow — but usually on FPGAs rather than ASICs. RTL, timing closure, board bring-up.

The honest close.

Understanding the entire flow — not just your stage — is what makes an engineer valuable over a career. Every senior engineer you'll meet has developed intuition for stages they don't personally own. Start building yours early.